Books

• V. Moshnyaga, T.Morimoto, K. Hashimoto, "Introduction to Microcomputers: Programming a High-Performance 8-bit PIC Microcomputer in C", Kyoritsu Shuppan, 188 pages, ISBN978-4-320-12485-1, 2022 (Printed in Japan).

Book Chapters

• V.G. Moshnyaga, "ICT Based Technologies for Safe Bathing: Challenges and Solutions", Chapter 5 (pp.79-142), An Introduction to Assistive technology , S.S. Senjam (Editor), Nova Science Publishers, ISBN 978-1-53618-9353, 250 pages, 2021.

• K.Kasman and V.G. Moshnyaga, "New Technique for Posture Identification in Smart Prayer Mat", (pp.19-31), Innovative Technologies and Services for Smart Cities, Subhas Mukhopadhyay and Tarikul Islam (Editors), MDPI, ISDN 978-3-03921-181-4, 214 pages, 2019.

• V.G. Moshnyaga, "Practical Guidelines for Design of Human-in-the-Loop Systems: Lessons Learned", Chapter 7 (pp.155-179), Practical Issues of Intelligent Innovations , V.Sgurev, V.Jotsov, J.Kacprzyk (Editors), Springer, ISBN 978-3-319-78436-6, 330 pages, 2018.

• O. Tanaka, T.Ryu, A.Hayashida, V.G.Moshnyaga, K.Hashimoto, "A Smart Carpet Design for Monitoring People with Dementia", Chapter 50 (pp.653-659), Progress in System Engineering, Advances in Intelligent Systems and Computing, H.Selvaraj, D.Zydek, G.Chmaj (Editors), Shpringer, ISBN 978-3-319-08421-3, 899 pages, 2015.

• V.G. Moshnyaga, "Display Energy Management based on Eye Tracking", Chapter 15 (pp.350-365), Sustainable ICT's and Management Systems for Green Computing, Wen-Chen Hu, and Naima Kaabouch (Editors), IGI Global, ISBN 978-1-4666-1839-8, 467 pages, 2012.

• V.G. Moshnyaga, "Understanding and exploiting user behavior for energy saving", Chapter 50 (pp.1145-1157), Handbook of Energy-Aware and Green Computing, Volume 2, I. Ahmad, S. Ranka (Editors), Chapman & Hall/CRC Computer and Information Science Series, CRC Press, Taylor & Francis Group, LLC, NY, ISBN 978-1-4398-5040-4, 1284 pages, 2012.

• V.G.Moshnyaga, "A Camera-Based Energy management of Computer Displays and TV Sets" Chapter 7, (pp.137-156), Energy Technology and Management, T.Aized (Editor), InTech, ISBN 978-953-307-742-0, 228 pages, 2011.

• V.G.Moshnyaga, and K.Inoue, "Low Power Cache Design" Chapter 8 (pp.8-1 - 8-21), Low-Power Processors and Systems on Chip, C. Piguet (Editor), CRC Press, Taylor & Francis Group, LLC, NY, ISBN 978-0-8493-6700-7, 2005.

• V.G.Moshnyaga, and K.Inoue, "Low Power Cache Design" Chapter 25 (pp.25-1 - 25-21), Low-Power Electronics Design, C. Piguet (Editor), Computer Engineering Series, CRC Press, Taylor & Francis Group, LLC, NY, ISBN 0-8493-1941-2, 2004.

  Journal Publications

• K.Hashimoto, M.Koyanagi, F.Hirayama, A.Takahama, V.Moshnyaga, "Development of Medication Adherence Monitoring System for People with Dementia" Fukuoka University Review of Technological Sciences, No.101-102, pp.51-58, 2018 (in Japanese).

• K.Kasman, and V.G.Moshnyaga, "New Technique for Posture Identification in Smart Prayer Mat", Electronics, MDPI, Vol.6, no.3, pp.61-74, Aug.2017.

• V.G.Moshnyaga, T.Ryu, O.Tanaka, and K. Hashimoto, "Low-Cost Assistive Technologies for In-Home Caregivers of People with Dementia", ICIC Express Letters, Part B: Applications , Vol.7, No.3, pp. 641-647, March 2016.

• P.White, T.Nishiuchi, V.Moshnyaga, K.Hashimoto, "A Study of Air-Conditioning Energy Saving Techniques in Fukuoka University Faculty of Engineering" Fukuoka University Review of Technological Sciences, No.97, pp.15-20, 2016 (in Japanese).

• V.G.Moshnyaga, T.Ryu, O.Tanaka, K.Hashimoto, "Identification of Basic Behavioral Activities by Heterogeneous Sensors of In-Home Monitoring System" in "Human Behavior Understanding", A.A.Salah, et al (eds), LNCS 9277, Springer, pp.160-175, Sep.2015.

• O.Tanaka, T.Ryu, A.Hayashida, V.G.Moshnyaga, K.Hashimoto, "A Smart Carpet Design for Monitoring People with Dementia" in "Progress in System Engineering, Advances in Intelligent Systems and Computing", H.Selvaraj, D. Zydek, G.Chmaj (eds),1089, Springer, pp.653-659, Jan.2015.

• T.Ando, V.G.Moshnyaga, K. Hashimoto, "FPGA Design of User Monitoring System for Display Power Control", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E95-A, No.12, pp. 2364-2372, Dec.2012.

• V.G.Moshnyaga, K. Hashimoto, T.Suetsugu, "A Camera-Driven Power Management of Computer Display", IEEE Transactions on Circuits and Systems for Video Technology, Vol.22, No.11, pp.1542-1553, Nov. 2012.

• T.Tsuzaki, K.Hashimoto and V.Moshnyaga "Implementation of Computer Mouse Functions by Gestures" Fukuoka University Review of Technological Sciences, No.89, pp.43-48, Sep. 2012 (in Japanese).

• T.Matsubara, V.G.Moshnyaga, K. Hashimoto, "A Low-Complexity and Low Power Design of 2D-Median Filter", ECTI Transactions on Computer Engineering, Computer and Information Technology, Vol. 5, No 2, pp. 1-9, Jan.2011.

• V.G.Moshnyaga, K. Hashimoto, T.Suetsugu, and S.Higashi, "A hardware implementation of the user-centric display energy management" , Integrated Circuit and System Design, Power, Timing Modeling and Simulation, J.Monteiro and R.V.Leuken(Eds), Revised Selected Papers, 20th International Workshop PATMOS 2009, Delft, The Netherlands, Sep.9-11, 2009, Springer, LNCS 5953, pp.56-65, 2010.

• V.G.Moshnyaga, "Untraditional Approach to Computer Energy Reduction", Integrated Circuit and System Design, Power, Timing Modeling and Simulation, L.Svenson and J.Monteiro (Eds), Revised Selected Papers, 18th International Workshop PATMOS 2008, Lisbon, Portugal, Sep.10-12, 2008, Springer, LNCS 5349, pp.82-92

• V. G. Moshnyaga, T. Yamanaka, "Multiplier Energy Reduction by Dynamic Voltage Variation", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E88-A, pp. 3548-3553, Dec.2005.

• R. Komiya, K. Inoue, V. G. Moshnyaga, and K. Murakami, "Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol.E88-A, no.4, pp.862-868, April 2005.

• V.Moshnyaga, "An Implementation of Data Reusable MPEG Video Coding Scheme", Transactions on Engineering, Computing and Technology, ISSN 1305-5313, Vol.2,pp. 257- 260, Dec. 2004.

• V. G. Moshnyaga and K. Masunaga, "Reduction of Background Computations in Block-Matching Motion Estimation," IEICE Transactions on Fundamentals of Electronics,Communications and Computer Sciences, Vol.E87-A, no.3, pp.539-546, March 2004.

• K. Inoue, V. G. Moshnyaga, and K. Murakami, "Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E86-A, no.4, pp.799-805, April 2003.

• V.G.Moshnyaga, "Reducing Switching Activity of Subtraction via Variable Truncation of the Most Significant Bits", The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol.33, No.1-2, pp.75-82, Jan.-Feb. 2003.

• V.G.Moshnyaga, "Reducing Energy Dissipation of Frame Memory by Adaptive Bit-Width Compression" IEEE Transactions on Circuits and Systems for Video Technology, Vol. 12, no.8, August 2002, pp.713-718.

• V.G.Moshnyaga, "Adaptive Bitwidth Compression for Low Power Video Memory Design" IEICE Transactions on Fundamentals in Electronics, Communications and Computer Sciences, Vol. E85-A, no.4, April 2002, pp.797-803.

• V.G.Moshnyaga, "Issue Queue Energy Reduction Through Dynamic Voltage Scaling", IEICE Transactions on Electronics, Vol. E85-C, no.2, Feb. 2002, pp.272-278.

• K.Inoue,V.G.Moshnyaga, K.Murakami, "Trends in High-Performance, Low-Power Cache Memory", IEICE Transactions on Electronics, Vol. E85-C, no.2, Feb. 2002, pp.304-314.

• K.Inoue,V.G.Moshnyaga, K.Murakami, "Omitting Cache Look-Up for High-Performance, Low-Power", IEICE Transactions on Electronics, Vol. E85-C, no.2, Feb. 2002, pp.279-287.

• V.G.Moshnyaga and H.Tsuji, "Reducing Cache Energy Dissipation through Dual-Voltage Supply", IEICE Transactions on Fundamentals in Electronics, Communications and Computer Sciences, Vol.E84-A, No.11, 2001, pp.2762-2768.

• V.G.Moshnyaga, "A New Computationally Adaptive Formulation of Block-Matching Motion Estimation", IEEE Transactions on Circuits and Systems for Video Technology, Vol.11, No.1, 2001, pp.10-16.

• V.G.Moshnyaga, "A Novel Computationally Adaptive Hardware Algorithm for Video Motion Estimation", IEICE Transactions on Electronics, Vol.E81-C,No.9, 1999, pp.1749-1754.

• V.G.Moshnyaga, N.Watanabe,K.Tamaru, "A Memory Based Architecture for Real-Time Motion Estimation", IEICE Transactions, Vol.J81-D-I, No.2, February 1998, pp.77-85 (in Japanese)

• V.G.Moshnyaga, N.Watanabe, K.Tamaru, "A Memory Efficient Array Architecture for Real Time Motion Estimation", Systems and Computers in Japan, Vol.29, No.9, pp.13-20, Scripta Technica 1998, pp.13-20.

• V.G.Moshnyaga, Y.Mori, H.Onodera, K.Tamaru, "A Performance-Driven Macro Block Placer for Architectural Evaluation of ASIC Designs", IEE Proceedings on Circuits, Devices and Systems, Vol.144, No.3, June 1997, pp.190-195.

• V.G.Moshnyaga, K.Tamaru, "A Floorplan Based Methodology for Data-Path Synthesis of Sub-micron ASICs" IEICE Transactions on Information and Systems, Vol. E79-D, No.10, October 1996, pp.1389-1396.

• V.G.Moshnyaga, Y.Mori, K.Tamaru, "Register-Transfer Module Selection for Sub-Micron ASIC Design", IEICE Transactions on Information and Systems, Vol. E78-D, No.3, March 1995, pp.252-255.

• V.G.Moshnyaga, H.Onodera, K.Tamaru, "Impact of Interconnect Behavior on Register-Transfer Synthesis of Sub-micron VLSI's: A Case Study", in Power and Timing Modeling for Performance of Integrated Circuits, D.Auvergne and R.Hartenstein (Eds.), IT Press Verlag, Brushsal, 1993, pp.55-64.

• V.Moshnyaga, K.Tamaru, H.Yasuura, "A Language for Designing Module Generators", IEICE Transactions on Information and Systems, Vol. E76-D, No.9, September 1993, pp.1066-1074.

• V.G.Moshnyaga, K.Tamaru, H.Yasuura, "Design of data-path module generators from algorithmic representations", in IFIP Transactions A-22 ``Synthesis for Control Dominated Circuits'', G.Saucier and J.Trilhe (Eds), Elsevier Science Publishers B.V. (North-Holland), 1993, pp.183-192.

• V.T.Frolkin, V.G.Moshnyaga, E.M.Tichomirova, S.I.Gyndya. "Hardware Accelerators - New Tools for LSI Logic Simulation", Foreign Electronics,, Moscow, ``Radio i sviaz'', 1990, No.6, pp.3-25 (in Russian).

• V.G.Moshnyaga, "A Combined Algorithm for Model Time Increment in LSI Logic Simulation Systems", Electronnoe Modelirovanie /Electronic Simulation/, Kiev, 1986, Vol.8, No.3, pp.97-100 (in Russian).

• V.G.Moshnyaga, E.M.Tichomirova, V.T.Frolkin, "Dynamic Hierarchical Simulation of LSI Digital Systems" Izvestia Vuzov SSSR - Radioelectronica /News from the USSR Universities - Radioelectronics/, Kiev, 1986, Vol.29, No.1, pp.8-12 (in Russian).

• V.T.Frolkin, E.M.Tichomirova, V.G.Moshnyaga, "Simulation of Large Scale Integration Circuits: The Status and Perspectives", Izvestia Vuzov SSSR -Radioelectronica / News from the USSR Universities -Radioelectronics/, Kiev, 1984, Vol.27, No.6, pp.17-31 (in Russian).

Patents

• S.Ikeda, V. Moshinyaga, K.Hashimoto, T.Hori, H.Kakeda,"Hospital Elopment/Wandering Detection System", Application No. 489-FU439, Patent Application 2022-106530, June 30, 2022 (Pending).

• T. Yoshida, K. Ishihara, Y. Matsuura, K. Matsumura, V.G. Moshnyaga, "Motion estimation unit", JP Patent, No. 4027513, Oct.19, 2007.

• S. Kumaki, T. Matsumura, H. Segawa, A. Hanami, V.G.Moshnyaga, "Data Processor and Processing Method Reduced in Power Consumption during Memory Access", US Patent, No. 6,918,002 B2, Jul.12, 2005.

• T. Yoshida, K. Ishihara, Y. Matsuura, V.G. Moshnyaga, "Motion estimation method and apparatus for interrupting computation which is determined not to provide solution", US Patent, No. 6,687,299 B2, Feb.3, 2004.

• T. Yoshida, V.G Moshnyaga, "Adaptive Difference Computing Element and Motion Estimation Apparatus Dynamically Adapting to Input Data", US Patent, No. 6,594,396 B1, July 15,2003.

• V.G. Moshnyaga, E.M. Tichomirova, V.T. Frolkin, A.V. Simakov, "A Device for Modeling of Flip-Flop Characteristics" Patent SU, No.1256052 IPC G06G7/25, 1986.

  International Conference Publications

• T. Imamura, V.G. Moshnyaga, K. Hashimoto, "Fall detection with a single Doppler radar sensor and LSTM recurrent neural network", Proceedings of the 2022 IEEE 65-th International Midwest Symposium on Circuits and Systems (MWSCAS 2022), Fukuoka, JAPAN, Aug.7-10, 2022.

  H. Akaike, S. Katsuta, S. Aramaki, V.G. Moshnyaga, K. Hashimoto, S. Ikeda, "Wandering Notification System for Caregivers of People with Dementia", Proceedings of the 2022 IEEE 65-th International Midwest Symposium on Circuits and Systems (MWSCAS 2022), Fukuoka, JAPAN, Aug.7-10, 2022.

• T. Imamura, V.G. Moshnyaga, K. Hashimoto, "Automatic fall detection by using Doppler-radar and LSTM-based recurrent neural network", Proceedings of the 2022 IEEE 4-th Global Conference on Life Sciences and Technologies (Life Tech 2021), Kyoto, JAPAN, March 10-12, 2022, pp.40-41.

• K.Nakajima, V.G.Moshnyaga, Hashimoto, "A comparative study of conventional and CNN-based implementations of facial recognition on Raspberry-Pi", Proceedings of the 2021 IEEE 19th World Symposium on APplied Machine Intelligence and Informatics , Herl'any, Slovakia, Jan. 21-23, pp.217-222.

• V.G.Moshnyaga, K.Hashimoto, T.Nogami, K.Nojima "A smart system for preventing people with dementia from falling from the chair",, Proceedings of the 2020 IEEE 2nd Global Conference on Life Sciences and Technologies (Life Tech 2020), Kyoto, Japan, March 10-12, 2020, pp.123-124.

• K.Hashimoto, H.Yoshino, V.G.Moshnyaga, "Development of Human Fall Detection System using Doppler Sensor and Machine Learning Technique", Proceedings of the 2019 Asia Pacific Conference on Robot IoT System Development and Platform (APRIS), Pattaya, THAILAND, Nov. 1-4, 2019, pp.1-2.

• H.Yoshino, V.G.Moshnyaga, and K.Hashimoto, "Fall Detection on a single Doppler Radar Sensor by using Convolutional Neural Networks", Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics (SMC 2019), Bari, ITALY, Oct. 6-9, 2019, pp.2875-2878.

• V.G.Moshnyaga, K.Hashimoto, T.Nogami, K.Nojima, "Design a Wireless Smart Chair System for People with Cognitive Deficiency", Proceedings of the 2019 IEEE 62-nd International Midwest Symposium on Circuits and Systems (MWSCAS 2019), Dallas, USA, Aug.4-7, 2019, pp.1219-1222.

• V.G.Moshnyaga, J.Shioyama, K.Hashimoto, "A Camera Based Approach to Prevent Fingerprint Hacking", Proceedings of the IEEE Workshop on Signal Processing Systems (SiPS 2019), Cape Town, SOUTH AFRICA, Oct.21-24, 2018, pp.235-240.

• S.Yamanaka and V.G.Moshnyaga, "New Method for Medical Intake Detection by Kinect", Proceedings of the 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS 2018), Windsor, CANADA, Aug.5-8, 2018, pp.218-221.

• A.Hayashida, V.G.Moshnyaga, and K.Hashimoto, "The Use of Thermal IR Array Sensor for Indoor Fall Detection", Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics (SMC 2017), Banff, CANADA, Oct.5-8, 2017, pp.594-599.

• A.Hayashida, V.G.Moshnyaga, and K.Hashimoto, "New Approach for Indoor Fall Detection by Infrared Thermal Array Sensor", Proceedings of the 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, Boston, MA, USA, Aug.6-9, 2017, pp.1410-1413

• Kasman, V.G.Moshnyaga, "A Smart Mat for Assisting Muslims in Praying", Proceedings of the 2017 International Conference on Consumer Electronics (ICCE), Las Vegas, USA, Jan.8-10, 2017, pp.481-484.

• V.Moshnyaga, M.Koyanagi, F.Hirayama, A.Takahama, K.Hashimoto, "A Medication Adherence Monitoring System for People with Dementia", Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics (SMC 2016), Budapest, HUNGARY, Oct.9-12, 2016, pp.194-199.

• V.Moshnyaga, "Lessons Learned from Developing Smart Systems", Proceedings of the SAI Intelligent Systems Conference 2016 (IntelliSys 2016), Sep.4-6, London, UK, pp. 85-90, 2016.

• Kasman, V.Moshnyaga, "New Technique for Unobtrusive Sensing of Human Postures by a Smart Prayer Mat", Proceedings of the 4th IIAE International Conference on Intelligent Systems and Image Processing 2016, Kyoto, JAPAN, Sep.8-12, 2016, pp.150-154.

• V.Moshnyaga, "Guidelines for Developers of Smart Systems", Proceedings of the 2016 IEEE International Conference on Intelligent Systems (IS'16), Sofia, BULGARIA, Sep.4-6, 2016, pp.455-460.

• N.Sumi and V.G.Moshnyaga, "A Novel Face Recognition for Smart Glasses", Proceedings of the 2016 IEEE Region 10 Symposyum (TENSYMP 2016), Bali, INDONESIA, May 9-11, 2016, pp.115-118.

• V.Moshnyaga, "Design of Minimum Complexity Reversible Multiplier", Proceedings of the 2015 IEEE Region 10 Conference TENCON, Macau, CHINA, Nov.1-4, 2016, pp.1-4.

• V.G.Moshnyaga, T.Ryu, O.Tanaka, K.Hashimoto, "Identification of Basic Behavioral Activities by Heterogeneous Sensors of In-Home Monitoring System", Proceedings of the 6th International Workshop on Human Behavior Understanding (HBU 2015), Osaka, JAPAN, Sep.8,2015, pp.160-175,

• T.Ryu, V.Moshnyaga, O.Tanaka, K.Hashimoto, "Sensing Technologies for In-Home Monitoring of People with Dementia", Proceedings of the 3rd IIAE International Conference on Intelligent Systems and Image Processing 2015, Fukuoka, Japan, Sep.2-5, 2015, pp.84-91.

• V.Moshnyaga, H.Nita "STG-based Detection of Power Virus Inputs in FSM", Proceedings of the 2015 IEEE 58th International Midwest Symposium on Circuits and Systems, Aug.2-5, 2015, Fort Collins, CO, USA, pp.692-695.

• V.Moshnyaga,T.Tanaka, T.Ryu, A.Hayashida, D.Sakamoto, Y.Imai, T.Shibata, "An Intelligent System for Assisting Family Caregivers of Dementia People", Proceedings of the 2014 IEEE International Symposium Series on Computational Intelligence (SSSCI), Dec 9-12, 2014, Orlando, FL, USA, pp.1-5.

• N.Sumi A.Baba, and V.Moshnyaga, "Effect of Computation Offload on Performance and Energy Consumption of Mobile Face Recognition", Proceedings of the 2014 IEEE Workshop on Signal Processing Systems (SIPS), Oct.20-22 2014, Belfast, UK, pp.19-25.

• A.Baba, N.Sumi and V.Moshnyaga, "Impact of Computation Offloading on Efficiency of Wireless Face Recognition", Proceedings of the 24-th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sept.29 - Oct.1 2014, Palma de Mallorca, SPAIN, pp.1-7.

• V.Moshnyaga, O.Tanaka, T.Ryu, A.Hayashida, "A Smart system for Monitoring People with Cognitive Impairment", Proceedings of the 2014 International Conference on Advanced Technology and Science (ICAT'14), August 12-15, 2014, Antalya, TURKEY,pp.1-4.

• V.Moshnyaga, O.Tanaka, T.Ryu, A.Hayashida, D.Sakamoto, Y.Imai, T.Shibata, "A Smart system for Home Monitoring of People with Cognitive Impairment", Proceedings of the 2014 IEEE International Humanitarian Technology Conference (IHTC), June 1-4, 2014, Montreal, QC, CANADA,pp.1-4.

• V.Moshnyaga, "Assessment of Software Lifecycle Energy and its Contribution to Green House Gas Emissions", Proceedings of the 2013 IEEE International Conference on Cloud and Green Computing (CGC'2013), Karlsruhe, GERMANY, Sep.30-Oct.2, 2013,pp.197-198

• V.Moshnyaga, "An Assessment of Software Lifecycle Energy", Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Karlsruhe, GERMANY, Sep. 9-11, 2013, pp.112-119.

• K.Imaizumi, V.Moshnyaga, "Network-Based Face Recognition on Mobile Devices" Proceedings of the 2013 IEEE International Conference on Consumer Electronics - Berlin (ICCE-Berlin), Sep.8-11, Berlin, GERMANY, pp. 406-409, 2013.

• V.Moshnyaga, "Lifecycle Energy Assessment of Mobile Apllications", Proceedings of the First International Workshop on Software Development Lifecycle for Mobile (DeMobile'13)>, in conjunction with ESES/FSE 2013, Aug. 18-26, Sankt-Petersburg, RUSSIA, pp.17-23, 2013

• K.Imaizumi, V.Moshnyaga, "Network-Based System for Face Recognition on Mobile Wireless Devices" Proceedings of the 2013 International Conference on Computer Design (CDES 2013), July 22-25, Las Vegas, NV, USA, pp.1-6, 2013.

• T.Ando, V.G.Moshnyaga, "A low complexity algorithm for eye-detection and tracking in energy constrained applications", Proceedings of the International Conference on Communications, Signal Processing,and Their Applications (ICCSPA 2013), Sharjah, UAE, Feb. 12-14, 2013.

• T.Ando, V.G.Moshnyaga and K.Hashimoto, "A low power FPGA implementation of eye tracking", Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2012), Kyoto, JAPAN, March 26-30, 2012 pp.1573-1576.

• T.Ando, and V.G.Moshnyaga, "FPGA Design of User Monitoring System for Display Power Control", Proceedings of the IEEE International Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI 2012), Beppu, Oita, JAPAN, March 8-9, 2012 pp.384-389.

• C.Lee and V.G. Moshnyaga, "Embedded System for Camera-Based TV Power Reduction", Proceedings of the Euromicro Conference on Digital System Design (DSD 2011), Oulu, FINLAND, Aug.30-Sep.2, 2011, pp.764-768.

• C.Lee and V.G. Moshnyaga, "TV Energy Management by Camera-Based Viewer Monitoring", Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), Rio de Janeiro, BRAZIL, May 15-18, 2011, pp.949-952.

• C.Lee, V.G. Moshnyaga and K.Hashimoto, "Embedded System for TV Power Reduction by Viewer Monitoring", Proceedings of the 2011 IEEE International Conference on Multimedia and Expo (ICME 2011), Barcelona, SPAIN, July 11-15, 2011, pp.1-4.

• T. Nagai, S. Aramaki and V.G.Moshnyaga, "The design object model for robotic assembly of mechanical components" , Proceedings of 2011 International Conference on Industrial Technology (2011 ICIT-SSST), Auburn, AL, USA, March 14-16, 2011, pp. 304-309.

• C.Lee, V.G. Moshnyaga and K.Hashimoto, "Using video technology for reducing TV energy", Proceedings of the 17th Korea-Japan Workshop on Frontiers of Computer Vision (FCV 2011), Ulsan, KOREA, Feb.9-11, 2011, pp.1-6.

• T.Matsubara, V.G.Moshnyaga, and K.Hashimoto, "A Low-Complexity and Low-Power Median Filter Design" , Proceedings of the 2010 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2010), Chengdu, CHINA, Dec.6-8, 2010, pp. 341-344.

• T.Matsubara, V.G.Moshnyaga, and K.Hashimoto, "A Low-Complexity Noise Removal Technique and its Hardware Implementation" , Proceedings of the IEEE TENCON 2010 - IEEE Region 10 Conference, Fukuoka, Japan, Nov.21-24, 2010, pp. 716-719.

• K.Hashimoto and V.G.Moshnyaga, "A New Approach for TCP/IP Offload Engine Implementation in Embedded Systems", Proceedings of the 44-th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, Nov.7-10, 2010 (6 pages).

• V.G.Moshnyaga, "A New Approach for Energy Management in User-Centric Applications", Proceedings of the International Green Computing Conference (IGCC 2010), Chicago, IL, USA, Aug. 15-18, 2010 (6 pages).

• K.Hashimoto and V.G.Moshnyaga, "A Cost-Effective TCP/IP Offload Accelerator Design for Network Interface Controller", Proceedings of the 2010 International Conference on Computer Design (CDES 2010), Las Vegas, NV, USA, July 12-15, CSREA Press, pp.153-159, 2010.

• V.G.Moshnyaga, "A New Energy Management Approach for User Centric Applications", Proceedings of the First International Conference on Green Circuits and Systems (ICGCS 2010), Shanghai, CHINA, June 21-23, 2010, pp.1-6.

• V.G.Moshnyaga, "The Use of Eye Tracking for PC Energy Management", Proceedings of the ACM Symposium on Eye-Tracking Research and Applications (ETRA 2010), Austin, TX, USA, March 22-24, pp.113-116, 2010.

• V.G.Moshnyaga, "Want to save Energy? - Put Intelligence into Systems", Recent Advances in Circuits, Systems, Electronics, Control and Signal Processing, Electrical and Computer Engineering Series, Pubished by WSEAS Press, pp.302-307.

• S.Yamamoto and V.G.Moshnyaga, "Algorithm Optimizations for Low-Complexity Eye-Tracking", Proceedings of the 2009 IEEE International Conference on Systems, Man and Cybernetics (SMC 2009), San Antonio, TX, USA, Oct. 2009, pp.cp18-22.

• V.G.Moshnyaga, K. Hashimoto, and T.Suetsugu, "Applying User Monitoring for Display Power management", Proceedings of the ICROS-SICE International Joint Conference 2009, Fukuoka, Japan, August 18-21, 2009,pp.3599-3604.

• V.G.Moshnyaga and K.Hashimoto, "An Efficient Implementation of 1-D Median Filter", Proceedings of the 52-th IEEE Midwest Symposium on Circuits and Systems (MWS2009), Cancun, Mexico, August 2-5, 2009, pp.451-454.

• T.Yamamoto and V.G.Moshnyaga, "A New Bit-Serial Architecture of Rank-Order Filter", Proceedings of the 52-th IEEE Midwest Symposium on Circuits and Systems (MWS2009), Cancun, Mexico, August 2-5, 2009, pp.511-514.

• V.G.Moshnyaga, K. Hashimoto, T.Suetsugu and S.Higashi, "A Hardware System for Tracking Eyes of Computer user", Proceedings of the 2009 International Conference on Computer Design (CDES 2009), Las Vegas, USA, July 13-16, 2009, pp.125-130.

• V.G.Moshnyaga, "Using Video Technology for Reducing Computer Energy", Proceedings of the 2009 IASTED International Conference on Advances in Computer Science and Engineering, Ed. V.Kachitvichyanukul, March 16-18, 2009, Phuket, Thailand, pp.193-198.

• V.G.Moshnyaga, K. Hashimoto, and T.Suetsugu, "A Hardware Design for Camera-Based User's Presence Detector", Proceedings of the 2008 IEEE International Conference on Systems, Man and Cybernetics (SMC 2008), Singapore, Oct.12-15, 2008, pp.429-432.

• V.G.Moshnyaga, K. Hashimoto, and T.Suetsugu, "FPGA design for user's presence detection", Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), Malta, Aug.31-Sep.3, 2008, pp.1316-1319

• V.G.Moshnyaga, K. Hashimoto, and T.Suetsugu, "A Hardware Design for Camera-Based Power Management of Computer Monitor" , Proceedings of the 11th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (DSD 2008), Parma, Italy, Sep.3-5, 2008, pp. 203-209.

• V.G.Moshnyaga, "How to Really Save Computer Energy?", Proceedings of the 2008 International Conference on Computer Design (CDES 2008), Las Vegas, USA, July 14-17, 2008, pp.89-95.

• V.G. Moshnyaga, "Data-Driven Techniques for Low-Energy Video Processing", Proceedings of the 41th IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, Nov.4-7, 2007.

• V.G.Moshnyaga, "Power Reduction Techniques for Digital Array Multipliers", Proceedings of the IEEE TENCON 2007, Taipei, Taiwan, Oct.30-Nov.2, 2007.

• V.G.Moshnyaga, "Static Macroblock Prediction for Low Complexity MPEG2", Proceedings of the IEEE TENCON 2007, Taipei, Taiwan, Oct.30-Nov.2, 2007.

• V.G. Moshnyaga, H. Vo, G. Reinman, M. Potkonjak, "Reducing Energy of DRAM/Flash Memory System by OS-Controlled Data Refresh", Proceedings of the 2007 International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, USA, May 27-30, 2007, pp.2108-2111.

• K. Hashimoto, V.G. Moshnyaga, K. Murakami, "Circuit Area-latency Optimization Technique for High-precision Elementary Functions", Proceedings of the 2006 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2006), Singapore, Dec. 4-7, 2006, pp.1436-1439.

• V.G. Moshnyaga, "Data-Driven Techniques for Low-Energy Video Processing", (Invited Talk), Proceedings of the 40th IEEE Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, Oct.29 - Nov.1, 2006.

• V.G. Moshnyaga, H. Vo, G. Reinman, M. Potkonjak, "Handheld system energy reduction by OS-driven refresh", in J.Vounckx (Ed.) Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2006, Montpellier, France, Sept. 2006, Proceedings, Springer, LNCS 3728, 753pages, pp.38-49.

• V.G.Moshnyaga, "A Wireless System for Energy Management of Household Electric Appliances", Proceedings of The 4th Int. Conference on Computing, Communications and Control Technologies (CCCT 2006), Orlando, FL, July 20-23, 2006.

• V.G.Moshnyaga, T.Migita, and K.Wakisaka, "Reducing computations in MPEG2 Video Decoder", Proceedings of the 2006 International Symposium on Circuits and Systems(ISCAS 2006), Kos, GREECE, May. 21-24, 2006.

• V.G.Moshnyaga, S.Yamaoka, "MPEG Complexity Reduction by Scene Adaptive Motion Estimation", Proceedings of the 2006 International Symposium on Circuits and Systems, (ISCAS2006), Kos, GREECE, May. 21-24, 2006.

• V.G.Moshnyaga, T. Migita, "An Algorithmic Enhancement for Reducing Computations of Bidirectional Motion Estimation", Proceedings of the IEEE Int. Workshop on Signal Processing Systems (SiPS2005), Athens, GREECE, Nov.2-4, 2005, pp.669-672.

• V.G. Moshnyaga and E. Morikawa, "LCD Display Energy Reduction by User Monitoring", Proceedings of the 2005 Int. Conference on Computer Design: VLSI in Computers & Processors (ICCD 2005), San Jose, CA, 2-5 Oct. 2005, pp.94-97.

• V.G.Moshnyaga, T.Migita, and K.Wakisaka, "Reduction of MPEG2 Decoding Computations" , Proceedings of the 3-rd IASTED Conf. on Circuits, Signals and Systems (SIP2005), Marina Del Ray, USA, Oct. 24-26, 2005, pp. 218-221.

• V.G. Moshnyaga and E. Morikawa, "Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring", in V.Paliouras, J.Vounckx, D.Verkest (Eds.) Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, Sept. 2005, Proceedings, Springer, LNCS 3728, 753pages, pp.528-539.

• V.G. Moshnyaga, "An Implementation of Data Reusable MPEG Video Coding Scheme", Proc. of the Int. Conf. on Signal Processing (ICSP 2004), Istanbul, Turkey, Dec.17-19, pp.257-260.

• K.Hamayasu, V.G. Moshnyaga, "Impact of Processor-Cache Bandwidth Variation on Processor Performance", Advances in Computer Systems, P-C. Yew and J.Xue (Eds.), Selected papers of 9th Asia-pacific Conference, ACSAC 2004, Beijing, China, Sept.2004, LNCS 3189, Springer pp. 212-225.

• K. Inoue, H. Tanaka, V.G.Moshnyaga, and K. Murakami, "A Low Power I-Cache Design with Tag-Comparison Reuse," Proc. of the International Symposium on System-On-Chip (SOC04), Tampere, Finland, Nov. 16-18, 2004.

• R. Komiya, K. Inoue, V.G. Moshnyaga, and K. Murakami, "Quantitative Evaluation of Leakage reduction Algorithm for L1 Data Caches", Proc. of the 2004 International SOC Design Conference, Seoul, Korea, Oct. 24-26, 2004, pp. 582-585.

• K. Tanamachi, K. Inoue, and V.G. Moshnyaga, "Designing a TCP/IP Core for Power Consumption Analysis," Proc. of the Fourth IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC04), Fukuoka, Japan, Aug.6-8, 2004, pp.412-413.

• V. G. Moshnyaga, K. Masunaga and N. Kajiwara "A Data Reusing Architecture for MPEG Video Coding", Proceedings of the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, CANADA, May 23-26, 2004, Vol.3, pp.III-797-III-800.

• T. Yamanaka and V. G. Moshnyaga, "Reducing Multiplier Energy by Data Driven Voltage Variation", Proceedings of the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, CANADA, May 23-26, 2004, Vol.2, pp.II-285-II-288.

• N. Kajiwara and V.G. Moshnyaga, "A Memory Reduction Approach for MPEG Video Coding", Proceedings of the 2003 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2003), Awaji Island, JAPAN, December 7-10, 2003, pp.399-402

• H. Takamura, K. Inoue, and V.G.Moshnyaga "Reducing Access Count to Register Files through Operand Reuse", in Advances in Computer Systems Architecture, Asia-Pacific Conference (ACSAC 2003), Aizu-Wakamatsu, Japan, September 2003, Proceedings, A.Omondi. S.Sedukhin (Eds.), Springer-Verlag, Berlin Heidenberg, 2003, LNCS 2823, pp.112-121.

• Y. Nishida, K. Inoue and V.G.Moshnyaga, "A Zero-Value Prediction Technique for Fast DCT Computation", in 2003 IEEE Workshop on Signal Processing Systems: Design and Implementation (SIPS2003), M.-H. Sunwoo and W.Sung (Eds), Seoul, KOREA, August 27-29, 2003, pp.165-170.

• M. Fujino and V.G.Moshnyaga, "Dynamic Operand Transformation for Low-Power Multiplier-Accumulator Design" , Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS2003), Bangkok, THAILAND, May 25-28, 2003, Vol.5. pp.345-348.

• J. Ohban, V.G.Moshnyaga, and K. Inoue, "Multiplier Energy Reduction Through Bypassing of Partial Products," Proceedings of the 2002 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS'02), Singapore, December 16-19, 2002,

• K. Inoue, V.G.Moshnyaga, and K. Murakami, "Reducing Power Consumption of Instruction ROMs by Exploiting Instruction Frequency," , Proceedings of the 2002 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS'02), Singapore, December 16-19, 2002,

• H.O. Boyo, M. Fujiwara, V.G.Moshnyaga and A. Boyo, "An Algorithm based on Joint Time-Frequency Analysis to Eliminate Noise from Stratospheric Laser Data", International Asia-Pacific Environmental Remote Sensing Symposium, Hangzhou, CHINA, October 25-27, 2002, Proceedings of SPIE, Vol.4891-100.

• H.O. Boyo, M. Fujiwara, V.G.Moshnyaga and A. Boyo, "Gabor Transform Detection and Subsequent Extraction of Inherently Embedded Noise in Stratospheric Lidar", Proceedings of International Conference on Opto-electronics and Laser Applications (ICOLA'02), Jakarta,INDONESIA, October 2-3, 2002, Vol. D, pp.D13-D-15.

• K. Inoue, V.G.Moshnyaga, and K. Murakami, "A Low Energy Set-Associative I-Cache with Extended BTB," Proceedings of the 2002 IEEE International Conference on Computer Design (ICCD'02), Freiburg, GERMANY, September 16-18, 2002, pp.187-192.

• H. Takamura, K. Inoue, and V.G.Moshnyaga, "Register File Access Reduction by Data Reuse", Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop PATMOS'2002, Seville, SPAIN, September 11-13, 2002. Proceedings, B. Hochet, A.J.Acosta, M.J.Bellido (Eds.), Springer-Verlag LNCS2451, pp.278-288, 2002.

• M. Fujino and V.G.Moshnyaga, "An Efficient Hamming Distance Comparator for Low-Power Applications," Proceedings of the 9-th IEEE International Conference on Electronics, Circuits and Systems (ICECS'2002), Dubrovnik, CROATIA, September 15-18, pp.641-644, 2002.

• K. Inoue, V.G. Moshnyaga, and K. Murakami, "A History-Based I-Cache for Low-Energy Multimedia Applications," Proceeding of the 2002 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'02), Monterey, CA, USA, August 12-14, 2002, pp.148-153.

• V.G.Moshnyaga, K. Inoue and M. Fukagawa, "Reducing Energy Consumption of Video Memory by Bit-Width Compression," Proceeding of the 2002 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'02), Monterey, CA, USA, August 12-14, 2002, pp.142-147.

• H.O. Boyo, M. Fujiwara, V.G. Moshnyaga and A. Boyo, "A DSP Application to Noise Localization and Extraction from Stratospheric Laser Echoes", Proceedings of IASTED International Conference on Signal and Image Processing (SIP 2002), Kauai, Hawaii, USA, August 12-14, 2002.

• V.G.Moshnyaga, "Reduction of Memory Accesses in Motion Estimation by Block-Data Reuse", Proceedings of the 2002 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP-2002), Orlando, FL, USA, May 13-17, 2002, Vol.3, pp.3128-3131.

• V.G. Moshnyaga and K.Masunaga, "Reducing Computation Complexity of Adaptive Motion Estimation through Binary Comparison", Proceedings of the 2002 IEEE International Symposium on Circuits and Systems (ISCAS 2002), Phoenix, AR, USA, May 26-29, 2002, Vol.2, pp.484-487.

• K. Inoue, V.G. Moshnyaga, and K. Murakami, "Dynamic Tag-Check Omission: A Low-Power Instruction Cache Architecture Exploiting Execution Footprints", in B.Falsafi, T.N.Vijaakumar (Eds), Power-Aware Computer Systems, Second International Workshop, PACS02, Cambridge, MA, USA, February 2002, Revised Papers, LNCS 2325, Springer, Vol.2, pp.18-32, 2002.

• V.G. Moshnyaga, "Adaptive Bit-width Compression for Low Energy Frame Memory Design", IEEE Workshop on Signal Processing Systems (SIPS'2001), Antwerpen BELGIUM, September 24-26, 2001, pp.185-192.

• V.G. Moshnyaga, "Energy Reduction in Queues and Stacks by Adaptive Bit-width Compression", ACM/IEEE International Symposium on Low-Power Electronic Design (ISLPED'2001) , Hantington Beach, CA, USA, August 6-8, 2001, pp.22-27.

• V.G. Moshnyaga, "Reducing Energy Dissipation of Complexity Adaptive Issue Queue by Dual Voltage", Workshop on Complexity-Effective Design hold in conjunction with International Symposium on Computer Architecture (ISCA-2001), Goteborg, SWEDEN, June 30, 2001.

• V.Moshnyaga, "Techniques for low energy processor architecture design", Proceedings of the 5th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, FL, USA, July 21-24, 2001.

• J.Tanaka, H.Shin-ei, V.G.Moshnyaga, "An Experimental Comparison of Adiabatic Logic Styles", Proceedings of the IEEE Internatioonal Conference on Circuits and Systems (SCS'2001), Iasi, ROMANIA, 9-11 July, 2001, pp.161-164.

• V.G. Moshnyaga, "Reducing switching activity of subtraction via bit truncation", Proceedings of the IEEE Internatioonal Conference on Circuits and Systems (SCS'2001), Iasi, ROMANIA, 9-11 July, 2001, pp.165-168.

• V.Moshnyaga, "Cache Energy Reduction by Dual Voltage Supply", IEEE International Symposium on Circuits and Systems (ISCAS'2001), Sydney, AUSTRALIA, May 6-9, 2001, Vol.4, pp.922-925.

• V. Moshnyaga, K.Inoue, Y.Yamamoto, "Reducing Activity of Multiplier-Accumulator Through Dynamic Operand Transformation" International Technical Conference on Circuits, Systems, Computers and Communications (ITCCSCC'2001), Tokushima, JAPAN, June 9-11, 2001 pp.143-146.

• V.G. Moshnyaga, H.Tsuji, "Reducing cache energy through dual voltage supply" Proceedings of the Asia-South Pacific Design Automation Conference (ASP-DAC'2001), Yokohama, JAPAN, January 2001, pp.302-305

• V.G. Moshnyaga, "Algorithmic and architectural transformaations for low energy video encoding", Proceedings of the 4th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, FL, USA, July 23-26, 2000, p.48-62.

• V.G. Moshnyaga, "A novel architecture for reducing background computations in block-matching motion estimation", Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP'2000), Istanbul, TURKEY, June 5-9, 2000, Vol.4, pp.3374-3377.

• V.G. Moshnyaga, K. Nakasima, "Reduction of background computations in adaptive block-matching motion estimation", Proceedings of the IEEE International Symposium on Circuits and Systems, (ISCAS'2000) Geneva, SWITZERLAND, 2000.

• V.G. Moshnyaga, N. Watanabe, "Techniques for bit-width truncation in video processing hardware", Proceedings of the 9-th International Workshop on Power and Timing Modeling, Optimization and Simulation of IC (PATMOS'99), Kos, GREECE, October 6-8, 1999, pp.241-248.

• V.G. Moshnyaga, "A New Architecture for Computationally Adaptive Full-Search Block-Matching Motion Estimation", Proceedings of the IEEE International Symposium on Circuits and Systems(ISCAS'99), Orlando, FL, USA, May 30- June 2, 1999, Vol.4, pp.219-222.

• V.G.Moshnyaga "New Techniques for Architectural Design of Low Power Video Processors", (Tutorial 2), The 6th IEEE International Conference on Electronics, Circuits and Systems, September 5-8, 1999, Pafos, CYPROS.

• V.G. Moshnyaga, "New Techniques for Low Power Architecture Design", Proceedings of the International Workshop on Multi-Architecture Low Power Design, Moscow, RUSSIA, July 1999.

• V.G. Moshnyaga, "An MSB Truncation Scheme for Low Power Video Processors", Proceedings of the IEEE International Symposium on Circuits and Systems, (ISCAS'99) Orlando, FL, USA, May 30- June 2, 1999, Vol.4, pp.291-294.

• V.G. Moshnyaga, "An Adaptive Block-Matching Algorithm for Motion Estimation", Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP'99), Phoenix, AR, USA, March 15-19, 1999, Vol.4, pp.3401-3404.

• V.G. Moshnyaga, "Architectural Techniques for Design of Low-Energy Video Encoders", (Invited paper), Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'98), Lyngby, DENMARK, October 6-8, 1998, pp.130-142.

• V.G. Moshnyaga, K. Suzuki, K. Tamaru, "A New Architecture for In-Memory Image Convolution", Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP'98), Seattle, WA, USA, May 12-15, 1998, Vol.5, pp.3001-3004.

• V.G. Moshnyaga, K. Suzuki, K. Tamaru, "Memory-Based Architecture for Real Time Convolution with Variable Kernels", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'98), Monterey, CA, USA, May 31-June 3, 1998, Vol.4, pp.89-92.

• V.G.Moshnyaga and K.Tamaru, "Energy Saving Techniques for Architecture Design of Portable Embedded Devices", Proceedings of the 10-th IEEE International ASIC Conference and Exhibit, Portland, OR, USA, September 7-10, 1997, pp. 163-167.

• S.Furusawa, V.G.Moshnyaga and K.Tamaru "A Combined Hardware Selection, Resource Sharing and Clock Optimization for Pipelined Data-Path Synthesis", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'97), HONG KONG, June 9-12, 1997, Vol.3, pp. 1588-1591.

• V.G.Moshnyaga and K.Tamaru, "A Memory Efficient Array Architecture For Real-Time Motion Estimation" , Proceedings of the IEEE International Parallel Processing Symposium, Geneva, SWITZERLAND, April 1-5, 1997, pp.28-32.

• V.G.Moshnyaga and K.Tamaru, "Effects of Technology Scaling on Area-Delay Characteristics of RTL Designs: A Case Study", Proceedings of the European Design & Test Conference, User Forum Paris, FRANCE, March 17-20, 1997, pp.75-80.

• V.G.Moshnyaga and K.Tamaru, "A Memory Efficient Array Architecture For Full-Search Block Matching Algorithm", Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP'97), Munich, GERMANY, April 20-24, 1997, Vol.5, pp.4109-4112.

• V.G.Moshnyaga and K.Tamaru, "A Placement Driven Methodology for High-Level Synthesis of Sub-micron ASICs", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'96), Atlanta, GA, USA, May 12-15, 1996, Vol.4, pp.572-575.

• S.Furusawa, V.G.Moshnyaga and K.Tamaru, "Integrated Hardware Selection, Resource Sharing and Clock Optimization for Pipelined Data-Path Synthesis", Proceedings of the Synthesis and System Integration of Mixed Technologies Workshop (SASIMI'96), Fukuoka, JAPAN, November 25-26, 1996, pp. 143-148.

• V.G.Moshnyaga, K.Tamaru, "Impact of Adding Schemes on Switching Activity of Digital Multipliers", in PATMOS'95: Power and Timing Modeling for Performance of Integrated Circuits, C.Piguet, W.Nebel (Eds.), BIS Verlag, 1995, pp.239-250.

• Y.Mori, V.G.Moshnyaga, H.Onodera, K.Tamaru, "A Performance-Driven Macro-Block Placer for Architectural Evaluation of ASIC Designs", Proceedings of the 8-th IEEE International ASIC Conference and Exhibit, Austin, TX, USA, September 18-23, 1995, pp. 233-236.

• V.G.Moshnyaga, F.Ohbayashi, K.Tamaru, "A Scheduling Algorithm for Synthesis of Bus-Partitioned Architectures", Proceedings of ASP-DAC'95/CHDL'95/VLSI'95, Makuhari Messe, JAPAN, August 29 - September 1, 1995, pp. 43-48.

• V.G.Moshnyaga, K.Tamaru, "A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS'95), Seattle, WA, USA, April 29 - May 3, 1995, pp. 1560-1563.

• V.G.Moshnyaga, K.Tamaru, "A Control-Flow Optimization Technique for High-Level Memory Management" , Proceedings of the 2-nd Asia Pacific Conference on Hardware Description Languages (APCHDL'94), Toyohashi, JAPAN, October 24-25, 1994, pp. 251-254.

• V.G.Moshnyaga, Y.Mori, H.Onodera, K.Tamaru, "Layout-Driven Module Selection for Register-Transfer Synthesis of Sub-micron ASIC's", Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD'93), Santa Clara, CA, USA, November 7-11, 1993, pp. 100-103.

• V.G.Moshnyaga, Y.Mori, K.Tamaru, "A RTL-Library Mapping Algorithm for Sub-micron ASIC Synthesis", Proceedings of the 3-d International Conference on VLSI and CAD, Taejon, KOREA, 15-17 November, 1993, pp. 211-214.

• V.G.Moshnyaga, Y.Mori, K.Tamaru, "Combined Module Selection and Performance-Driven Placement in Register-Transfer Synthesis of Sub-micron ASIC's", Proceedings of the Synthesis and Simulation Meeting and International Interchange ``SASIMI'93'', Nara, JAPAN, 20-22 October 1993, pp. 130-137.

• V.G.Moshnyaga and H.Yasuura, "A Language for Designing Module Generators", Proceedings of the Synthesis and Simulation Meeting and International Interchange ``SASIMI '92'', Kobe, JAPAN, April 1992, pp. 383-392.

• V.G.Moshnyaga, H.Yasuura, "Data-Path Modules Design from Algorithmic Representations", Proceedings of the WG 10.5 IFIP Workshop on Synthesis, Generation and Portability of Library Blocks for ASIC Design, Grenoble, FRANCE, March 1992, pp.22-30.

• V.G.Moshnyaga and H.Yasuura, "A Language for Designing Module Generators", Proceedings of the "Russian Workshop'92", Moscow, Russia, June 1992, pp. 83-92.

• V.G.Moshnyaga, "Computer-Aided Hardware-Software Codesign: Status and Directions", Proceedings of the International Congress of Romanian-American Academy of Science, Chisinau, MOLDOVA, 10-16 July 1993, pp.132-135.

  Domestic Conference Publications

• M.Shimizu, K.Hashimoto, T.Imamura, V.Moshnyaga "Design of 24GHz Band Doppler Sensor Unit for Human Fall Detection", 2022 General Conference of the Institute of Electronics, Information and Communication Engineers,B-19-16, March 15-18, 2022, (in Japanese).

• T.Imamura, K.Hashimoto, V.Moshnyaga, "Refined System for Automatic Fall Detection by using Doppler Sensor and LSTM" General Conference of the Institute of Electronics, Information and Communication Engineers,B-19-17, March 15-18, 2022, (in Japanese).

• K.Hashimoto, H.Yoshino, V.Moshnyaga, "Development of Fall Detection System by using Doppler Sensor and Machine learning", Proceedings of the Embedded System Symposium 2019 (ESS 2019), Nov. 2019. (in Japanese)

• K.Hashimoto, V.Moshnyaga, M.Koyanagi, F.Hirayama, A.Takahama, "Development of medication Adherence System for People with Dementia", Proceedings of the 81-st National Convention of IPSJ, March 14-16, pp.4-409-4-410, 2019.(in Japanese)

• H.Yoshino, K.Hashimoto, V.Moshnyaga, "A Fall Detection Technique based on Doppler Sensor and Machine Learning", Proceedings of the 81-st National Convention of IPSJ, March 14-16, pp.4-437-4-438, 2019.(in Japanese).

• P.White, K.Hashimoto, N.Sumi, A.Hayashida, V.Moshnyaga, "A Smart Door System Development as a Project for Pracice-Oriented Short-Term Problem Based Learning (PBL)", Proceedings of the Embedded System Symposium 2015 (ESS 2015), Nov. 2015, pp.127-128. (in Japanese)

• P.White, V.Moshnyaga, K.Hashimoto, "A System for Energy Measurement of Software Applications", The 66th Joint Conference on Electrical, Electronics and Information Engineers in Kyushu, Sep.2014, 13-2A-14.

  N.Sumi, P.White, A.Baba, V.Moshnyaga, K.Hashimoto, "A Comparion of Power Consumption of Offloading Techniques in Mobile Face Recognition System", The 66th Joint Conference on Electrical, Electronics and Information Engineers in Kyushu, Sep.2014, 08-1P-04 (in Japanese).

• T.Yamamoto, V. Moshnyaga, K.Hashimoto, "A Trial PBL Using Digital Hardware R\& D-Oriented Theme," Proceedings of the Embedded System Symposium 2011 (ESS 2011), Nov. 2011, pp.6-1 - 6-10. (in Japanese)

• T. Ando, K.Hashimoto, and V.G. Moshnyaga, "Display Power Management System by User' Eye Detection " Proceedings of the 25-th (Karuizawa) Workshop on Circuit and Systems, Apr. 2011, pp.1-6. (in Japanese)

• T.Yamamoto, V. Moshnyaga, K.Hashimoto, "A New Design of Memory-Based Median Filter," Proceedings of the 24-th (Karuizawa) Workshop on Circuit and Systems, Apr. 2010, pp.1-6. (in Japanese)

• K.Hashimoto and V. Moshnyaga, "High-Throughput TCP/IP Offload Engine to realize Ultra-Low-Power Embedded System," Proceedings of the IEICE Spring Conference, Sendai, March 2010. (in Japanese)

• K.Hashimoto, V.G. Moshnyaga and T.Suetsugu, "FPGA based Design of PC User Monitoring System", Proceedings of IEICE Spring Conference, pp.91-92, March 2008 (in Japanese).

• K.Hashimoto and V.G. Moshnyaga, "Design Technique of Low-Size and High-Performance Hardwired TCP/IP Offload Engine for Embedded Systems," Technical Report of IEICE, vol. 107, no. 559, DC2007-94, pp. 61-66, March 2008 (in Japanese)

• V.G. Moshnyaga and K.Hashimoto, "A video-camera based approach for reducing energy of computer display", Proceedings of 2006 Annual Conference of the Illuminating Engineering Institute of Japan, pp.97-98, August 23-24, 2007.

• T.Migita and V.G. Moshnyaga, "Optimization of Bidirectional Motion Estimation by Zero-Value Prediction", Forum on Information Technology 2006, pp.335-336, Sep. 5-7, 2006. (in Japanese).

• S.Yamaoka, V.G. Moshnyaga, "A Scene Adaptive Technique for MPEG2 Motion Estimation", Forum on Information Technology 2006, pp.337-338, Sep. 5-7, 2006. (in Japanese).

• K. Hashimoto, V.G. Moshnyaga, K.Murakami, "Circuit area-latency optimization technique for high-precision elementary functions", Proceedings of the 19th (Karuizawa) Workshop on Circuit and Systems, pp. 217-222, Apr. 24-25, 2006　(in Japanese).

• H.Tanaka, K. Inoue, and V.G. Moshnyaga, "Adaptive Way-Predicting Cache for Low-Power Consumption", IEICE Technical Reports, VLD2004-139, ICD2004-235, Vol.104, no.709, pp.13-18, March 2005 (in Japanese).

• R. Komiya, K. Inoue, V. G. Moshnyaga, and K. Murakami, "A Cache Management Technique via Sleep-Hit Locality to Alleviate Performance Impact of Low-Leakage Caches" IPSJ Technical Reports 2004-ARC-160, pp.95-100, Dec. 2004 (in Japanese).

• R. Komiya, K. Inoue, V. G. Moshnyaga, and K. Murakami, "A Quantitative Evaluation of Cache Leakage Reduction Algorithms on Multi-Thread Processors", Forum on Information Technology 2004, pp.283-284, Sep. 2004 (in Japanese).

• K. Tanamachi, K. Inoue, and V. G. Moshnyaga, "Designing a TCP/IP Core for Power Consumption Analysis", Forum on Information Technology 2004, pp.217-218, Sep. 2004 (in Japanese).

• R. Komiya, K. Inoue, V. Moshnyaga, and K. Murakami, "Quantitative Evaluation of Cache Leakage Reduction Algorithm," Proc. of the 17th (Karuizawa) Workshop on Circuit and Systems, pp.235-240, Apr. 2004 (in Japanese).

• H. Tanaka, K. Inoue, V. Moshnyaga, and K. Murakami, "Design of A Low Power Instruction Cache with Tag-Comparison Reuse", Proc. of the 17th Workshop on Circuit and Systems in Karuizawa, pp.229-234, Apr. 2004 (in Japanese).

• H. Tanaka, K. Inoue, V. G. Moshnyaga, and K. Murakami, "Design and Evaluation of A History-Based Tag-Comparison Cache", IPSJ General Conference, pp. 83-84, Mar. 2004 (in Japanese).

• T.Yamanaka, V.G.Moshnyaga， "A Technique for Multiplier Energy Reduction by Dual Voltage Supply," Proceedings of 2003 Electrical Society (Kyushu Branch), September 2003, p.09-1P-10. (in Japanese).

• Y. Nishida, K. Inoue, and V. Moshnyaga, "Reducing the DCT operations based on zero-value prediction," Proceedings of the 16-th (Karuizawa) Workshop on Circuit and Systems, pp.147-152, Apr. 2003. (in Japanese)

• T. Iwasa, H. Tanaka, K. Inoue, and V. Moshnyaga, "On-Chip Memory Systems for Low Power, Secure System-on-a-Chips," Proc. of the 6th System LSI Workshop, pp.259-262, Nov. 2002. (in Japanese).

• H. Tanaka, K. Inoue, V. G. Moshnyaga, and K. Murakami, "Design and Evaluation of a History-Based Tag-Comparison Cache," IPSJ General Conference -1-, pp.83-84, March 2003. (in Japanese)

• H.Takamura, K. Inoue, and V. Moshnyaga, "Reducing Register File Energy though Operand Data Reuse," IPSJ SIG Notes (SWoPP2002), 2002-ARC-149, vol.2002, no.81, pp.13-18, Aug. 2002. (in Japanese)

• K. Inoue, V.G. Moshnyaga, and K. Murakami, "Energy Efficiency of History-Based Tag-Comparison I-Caches for Media Applications," IEICE Technical Report, CPSY2002-1-11, vol.102, no.27, pp.55-60, Apr. 2002. (in Japanese)

• K. Inoue, V. Moshnyaga, and K. Murakami, "A Low Power I-Cache Architecture based on Tag Comparison Reuse," Proc. of the 15-th (Karuizawa) Workshop on Circuit and Systems, pp.571-576, Apr. 2002.(in Japanese)

• K. Inoue, V.G. Moshnyaga, and K. Murakami, "Reducing Power Consumption of Instruction ROMs by Exploiting Instruction Frequency (in Japanese)," Proceedings of the 15-th (Karuizawa) Workshop on Circuit and Systems, pp.pp.565-570, Apr. 2002.(in Japanese)

• K. Inoue, V. Moshnyaga, and K. Murakami, "A Low Power Cache Memory Architecture based on Tag Compare Reuse", IEICE Technical Report, CPSY 2001-61-74, vol.101, no.473, pp. 49--54, Nov. 2001 (in Japanese).

• Fukagawa, K. Inoue, and V. Moshnyaga, "Reducing Power Consumption of Video Memory ｔhrough Data Compression," IEICE Technical Report, CPSY 2001-61-74, vol.101, no.473, pp. 55-60, Nov.2001 (in Japanese).

• H. Tsuji, K. Inoue, and V. Moshnyaga, "Reducing Energy Dissipation of Complexity Adaptive Issue Queue by Dual Voltage Supply," IEICE Technical Report, CPSY 2001-61-74, vol.101, no.473, pp. 61-66, Nov.2001 (in Japanese).

• H.Tsuji, V.G.Moshnyaga, "Reducing cache energy consumption using two voltage supplies", Proceedings of the 13-th Karuizawa Workshop on Circuits and Systems, April 24-25, 2000, pp.549-554. (in Japanese).

• K.Fujino, N. Tsuruta, V.G.Moshnyaga "On Image Binarization for Improving Accuracy of Connection Measurement from Ion-Beam Microscope Images", Proceedings of 1999 Joint Conference of Electric Society (Kyushu Branch), October 1999, pp.642. (in Japanese)

• K.Nakasima and V.G.Moshnyaga, "A Data-Driven Block-Matching Motion Estimation" Proceedings of 1999 Joint Conference of Electric Society (Kyushu Branch), October 1999, pp.783. (in Japanese)

• H.Sin-ei and V.G.Moshnyaga, "Design of Adiabatic Circuits from Karnaugh Maps" Proceedings of 1999 Joint Conference of Electric Society, (Kyushu Branch), October 1999, pp.747. (in Japanese)

• N.Watanabe, V.G.Moshnyaga, K.Tamaru "A Processor Array Architecture with Distributed Memory for Detecting Motion Vectors" Proceedings of The Second System LSI (Biwako) Workshop (1998). (in Japanese)

• K.Suzuki, V.G.Moshnyaga, K.Tamaru, "A Memory-Based Architecture for Real Time Convolution with Variable Kernels", Proceedings of the 1998 Karuizawa Workshop , April 19-21, 1998, (in Japanese).

• N.Watanabe, V.G.Moshnyaga, K.Tamaru, "A Memory Efficient Aray Architecture for Motion Detection", Technical Report of IEICE, ICD98, CPSY98-7, FTS98-7, April 1998, pp.49-56, (in Japanese).

• N.Watanabe, V.G.Moshnyaga, K.Tamaru, "A Processor Aray Architecture for Detecting Motion Vector with Distributed Memory", Proceedings of the 1997 Electronics Society Conference of IEICE, September 3-6, 1997, Waseda Univ., Tokyo, pp.113-114, (in Japanese).

• M.Ukai, V.G.Moshnyaga and K.Tamaru, "A technique for Ordering of Data-Flow Graph Transformations from Algorithmic Notations", Proceedings of the DA Symposium'97 , July 10-12, 1997, IPSJ, Vol.97, pp.155-160, (in Japanese).

• V.G.Moshnyaga and K.Tamaru, "A New Memory Based Architecture and Its Application For Real-Time Motion Estimation", Scientific Research on Priority Areas "Ultimate Integration of Intelligence on Silicon Electronic Systems", (269), 1997, pp.34-40.

• V.G.Moshnyaga and K.Tamaru, "A Placement Driven Methodology for Data-Path Synthesis of Deep Sub-micron ASICs", Proceedings of the DA Symposium'96 , August 29 - 31, 1996, IPSJ, Vol.96, pp.251-256.

• S.Furusawa, V.G.Moshnyaga, H.Onodera, K.Tamaru, "An Algorithm for Combined Module Selection and Resource Sharing in Pipelined Data-Path Synthesis", Technical Report of IEICE, VLD95-135, ICD95-235 (1996-03), pp.45-51, (in Japanese).

• V.G.Moshnyaga, S.Furusawa, K.Tamaru, "Timing Analysis in Register-Transfer Synthesis of Sub-Micron Circuits", Proceedings of the DA symposium'94, August 25-27, 1994, Vol.94, No.5, pp.15-20.

• S.Furusawa, V.G.Moshnyaga, K.Tamaru, "Incorporating Wiring Delays in Register-Transfer Timing Analysis", Proceeding of the 1994 IEICE Fall Conference, IEICE, September 26-29, 1994, pp.66-67, (in Japanese).

• V.G.Moshnyaga, Y.Mori, K.Tamaru, "Layout-Driven Module Selection for Register-Transfer Synthesis of Sub-micron ASIC's", Proceedings of the DA symposium '93, IPSJ, vol.93, no.5, August 1993, pp.9-12.

• V.G.Moshnyaga and K.Tamaru, "A Register Allocation Algorithm for Bottom-Up Data Path Synthesis" Proceedings of the DA symposium '92, IPSJ, Vol.92, no.4, August 1992, pp.5-8.

• V.Moshnyaga, H.Yasuura, "A Language for Designing of VLSI Module Generators", Report of Technical Group on Design Automation, IPSJ 60-2, December 1991, pp.9-15.

• Moshnyaga V.G.,Gyndya S.I., "The Use of a Hardware Accelerator for Functional-Logic Simulation of Digital LSIs" Proceedings of the Republican Conference on Computer Design, Kishinev, 1989, (in Russian).

• Moshnyaga V.G. "Automated Design of LSI Logic Structures on Mini-Workstations", Proceedings of the Republican Conference Republican Conference "Computer Design Techniques", Kishinev, 1989, (in Russian).

• Moshnyaga V.G., Myrza V.M., "An Algorithm for Synthesis of Digital LSI Structures", Proceedings of the Republican Conference "25 anniversary of Kishinev Polytechnical Institute", Kishinev, 1989, (in Russian).

• Moshnyaga V.G.,Abashkin G.A.,Russu V.V., "A Program Set for Data-Base Informational Support", Proceedings of the Republican Conference "25 anniversary of Kishinev Polytechnical Institute", Kishinev, 1989, (in Russian).

• Moshnyaga V.G.,Beshliu V.A.,Varzari B.V. "Functional-Logic Simulation of LSI Circuits on Mini-Computers", Proceedings of the Republican Conference "25 anniversary of Kishinev Polytechnical Institute", Kishinev, 1989, (in Russian).

• Moshnyaga V.G. "Organization of an Interactive Bottom-Up Design System", Proceedings of the Republican Conference "Interactive Tools for Design Automation", Kishinev, 1988, (in Russian).

• Moshnyaga V.G.,Beshliu V.A.,Varzari B.V. "Program Tools for Development of Interactive Systems", Proceedings of the Republican Conference "Interactive Tools for Design Automation", Kishinev, 1988, (in Russian).

• Dmitruk A.V., Moshnyaga V.G., "Automated Design of a Specialized Data Base for Radioelectronic CAD Systems", Proceedings of the 9-th Moscow Aviation Institute Conference, Moscow, 1987 (in Russian).

• Moshnyaga V.G., Dmitruk A.V., Zaviyalova V.V., "A Multivalue Logic Simulation of Digital Devices", Proceedings of the 9-th Moscow Aviation Institute Conference,, Moscow, 1987 (in Russian).

• Moshnyaga V.G., "A Functional-Logic Simulation System for Mini-Computer", Proceedings of the All-Union Conference ''Design Automation Systems for High Performance Micro- and Mini-Computers'', Voronej, 1989, (in Russian).

• Frolkin V.T., Tichomirova E.M., Moshnyaga V.G., Dmitruk A.V., "An Interactive System for Multilevel Hierarchical Simulation of Digital LSI Devices on Mini-Computers" Proceedings of the All-Union Conference "Theoretical and Applicative Problems of Design and Maintenance of Radioelectronic and LSI CAD Systems", Moscow, 1986, (in Russian).

• Moshnyaga V.G., "Models and Method for Structural Design of Digital LSIs", Proceedings of the All-Union Symposium "Information Processing and Computers", Moscow, Nauka, 1986, (in Russian).

• Frolkin V.T., Tichomirova E.M., Moshnyaga V.G., "Principles of Automated Bottom-Up Synthesis of LSI Digital Systems", Proceedings of the All-Union Conference ''The State of the Art and Perspectives in Microelectronics'', Minsk, 1985, (in Russian).

• Frolkin V.T., Moshnyaga V.G., Tichomirova E.M., "A Logic Simulation System for Computer-Aided Design of LSI Circuits", Proceedings of the All-Union Conference "Theoretical and Technical Aspects of Design, Implementation and Maintenance of Radioelectronic CAD Systems", Moscow, 1984, (in Russian).

• Moshnyaga V.G., "Automated Logic Analysis of Digital IC from Electrical Representations", Proceedings of the 7-th Moscow Aviation Institute Conference, 1984, (in Russian).

  Thesis

• Moshnyaga V.G. "Models and Algorithms for Automated Synthesis and Evaluation of Digital LSI Structures at Functional-Logic Design Level", (PhD) Thesis, Moscow Aviation Institute, Moscow, 1986, (in Russian).

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Last updated April 2015